Huawei Ascend 920 will be released in the second half of the year, achieving the domestic substitution of Nvidia H20.
21/04/2025
GMT Eight
It is reported that Huawei has developed the successor of the Ascend 910CAI chip - the Ascend 920, and plans to officially release it in the second half of 2025. According to the latest market news, Huawei has arranged to start mass production of this next-generation AI semiconductor product in the second half of this year. Many industry experts believe that the Ascend 920 chip is expected to fill the gap left by the NVIDIA H20 chip in the Chinese market due to the latest US restriction measures.
On the 15th local time, the US Department of Commerce announced new export licensing requirements for NVIDIA H20, AMD MI308, and equivalent chips exported to China. Under US export controls, manufacturers must obtain a license to export AI chips to China. It is understood that China is a key market for H20 chips. After this ban, the export restrictions on H20 chips will be indefinitely effective. At this time, the appearance of the Ascend 920 is not only expected to break NVIDIA's monopoly in the field of AI chips but also provide stronger computing power support for the development of China's AI industry, promoting the application and innovation of Chinese AI technology in more fields.
According to SevenTech, the specifications and performance characteristics of Huawei Ascend 920 AI chip are as follows:
Process Technology: The Ascend 920 chip will be based on Semiconductor Manufacturing International Corporation's 6nm (N+3 node) process technology.
Computing Power and Memory Bandwidth: With HBM3 memory modules, it can provide 900TFLOPS of BF16 computing power and 4000GB/s of memory bandwidth.
Architecture and Training Efficiency: It continues the design architecture of Ascend 910C, with training efficiency reportedly improved by 30%-40% compared to 910C, and performance is expected to surpass NVIDIA H20.
Interface Support: This new chip supports PCIe5.0 and next-generation high-throughput interconnect protocols, optimizing resource scheduling and cross-node collaboration.
Enhanced Features: It further enhances the tensor operation accelerator, optimizing for Transformer and MoE models to better meet the training needs of larger and more complex models.