TSMC develops new technology for 2D transistors, breaking through the interface bottleneck of advanced semiconductor materials.

National Yang Ming Chiao Tung University in Taiwan and TSMC's R&D team have made new progress in the field of two-dimensional semiconductors, proposing an atomic-scale interface engineering technology that can maintain high electrical performance while reducing transistor size, promising to advance the development of next-generation low-power semiconductor technology. The relevant research findings have been published in Nature Electronics. The research team stated that two-dimensional semiconductor materials, which are only a single atom thick, possess excellent electrical properties and are viewed as a potential material to break through the limitations of silicon-based chips. However, when manufacturing transistors, defects can easily occur at the interface between the ultra-thin insulating layer and the semiconductor, leading to electron scattering and creating a bottleneck in enhancing transistor performance. The researchers improved the quality of the material interface by constructing an ultra-thin aluminum oxide interface layer on the surface of monolayer molybdenum disulfide semiconductors, combined with a high-k dielectric hafnium oxide gate dielectric, allowing the transistor to achieve both stronger electrical control capabilities and higher carrier mobility.