The update on the Tao Law paper is here, and the interpretation has arrived.

On September 4, He Tingbo, the head of Huawei's semiconductor division, updated the (Tao) law paper. Previously, on May 25, Huawei released version 1.0 of the Tao Law, and on July 4, it updated to version 2.0. Within less than four months, Huawei has published academic papers on the Tao Law three times. The latest paper, "Huaweis Chip Was Supposed to Melt?" addresses concerns regarding heat issues in 3D stacked chips. It mentions that heat is the most troubling hidden concern under the Tao Law. Within the chip, the primary energy consumption does not stem from computation itself but from data transmission. Externally, it is assumed that the increase in transistors per unit area after folding would inevitably cause a spike in power density, leading to more heat and higher energy consumption. However, in fact, through circuit folding, the typical core wire length has been reduced by 20%, and the length of critical path wires has been shortened by 70%, with the number of the most power-consuming wiresclock buffershalved. Additionally, the increase in the number of transistors achieved through circuit folding can be used to build more parallel cores, allowing each core to operate at lower voltage and clock frequency, providing more flexibility. The reduction in power consumption of the Kirin chip does not come from less computation, but from reduced data transmission. Actual test results show that compared to the Kirin 9030 Pro, the NPU, GPU, CPU P-core, DSP, and other modules of the Kirin 2026 can achieve lower frequencies, voltages, and power density while maintaining the same performance. Moreover, when running at full speed, a significant performance improvement is realizedthe transistor density of the Kirin 2026 chip has increased from about 155 million per square millimeter to 238 million, a 55% increase; at the same level of performance, NPU power consumption has decreased by 66%, GPU consumption by 58%, and CPU performance cores by 41%. The NPU is particularly notable: with 29 TOPS of computing power remaining unchanged, frequency dropped by 63%, voltage decreased from 0.85V to 0.55V, and power density fell by 73%. In response to localized high heat, Huawei's solutions focus on two aspects. First, the folding reduces the source power density, preventing local overheating. Second, by actively conducting thermal distribution during the design phase, modules that generate the most heat are placed in locations with the best thermal dissipation. However, folding is not a cure-all but rather a system engineering process that requires iteration. He Tingbo clearly pointed out that Tao is a law of time scaling, not energy scaling. If designers use all the time saved to increase frequency, the chip may end up consuming more power. Greater challenges still exist, including engineering issues such as mixed bonding spacing, wafer warping, alignment accuracy, and EDA tool adaptation, which will require ongoing efforts over the next three to five years. Although heat dissipation is alleviated due to the overall power consumption reduction, the underlying heat conduction issues have not disappeared. According to the latest report from Sinolink, Huawei's Tao Law chips are transitioning from 2D integration to 3D integration, with increases in process steps, interconnect quantity, and manufacturing complexity. This is seen as a positive boon for semiconductor equipment, with backend testing being a more direct incremental focus of the Tao Law. Front-end equipment benefits from domestic storage and advanced logic capacity expansion, while the Tao Law is expected to accelerate downstream expansion rates, leading to a comprehensive increase in demand for etching, thin film deposition, coating, developing, and bonding equipment. Backend testing is the more direct incremental focus of the Tao Law. The increase in chip stacking layers and interconnects requires enhancements in testing complexity, testing duration, and yield management, leading to a multiplicitous increase in chip CoT (cost of test) and driving demand for ATE, sorting machines, probe stations, SLT, and aging equipment. CITIC Securities indicated that Huawei's logical folding represents more of an innovation in design philosophy and pathways rather than a one-time solution, suggesting a focus on Fab, CP testing, and new equipment segments. In terms of Fab: The Tao Law directly drives demand for advanced process wafers, and the design innovations under the Tao Law primarily arise from the collaborative R&D of front-end fabs. In terms of CP testing: More wafers will lead to increased demand for probe cards, probe stations, and testing machines. The most apparent process direction driven by the Tao Law is ultra-fine pitch mixed bonding. This article is reprinted from "Cailian Press," author: Song Ziqiao, GMTEight editor: Xu Wenqiang.